Memory devices such as, for example, semiconductor random access memory (RAM) circuits store logic states by applying either high or low voltage levels to memory cell transistors that comprise a memory cell array. As an example, flash memory cells store a charge on a floating gate that may, for example, be doped polysilicon. The stored charge changes a threshold voltage (Vt) of the memory cell. In a “read” operation, a read voltage is applied to the gate of the memory cell, and the corresponding indication of whether the memory cell turns on (e.g., conducts current) indicates the programming state of the memory cell. For example, a memory cell that conducts current during the “read” operation may be assigned a digital value of “1,” and a memory cell that does not conduct current during the “read” operation may be assigned a digital value of “0”. Charge may be added to and removed from the floating gate to program and erase the memory cell (e.g., to change the memory cell value from “1” to “0”).
In order to control the application of voltage to the gate lines of selected cells in a memory cell array, gate line (or word line) voltage control circuits are typically employed. In general, memory cells are accessible by applying activation voltages to word lines and bit lines (drain lines). In this regard, word lines are typically used to activate memory cells and bit lines provide data to or retrieve data from activated memory cells. In a word line voltage control circuit, high and low (or negative) voltage levels may be applied to selected word lines of a memory cell array by a decoder circuit (e.g., a word line driver) in order to activate selected memory cells. In other words, when memory access is desired, an activation voltage may be applied to the corresponding word line by the word line driver to perform the desired function (e.g., read or write). In some cases, when memory access is not needed, the word line driver may apply a deactivation voltage to cease memory access function.
Although the function of word line drivers, as generally described above, is relatively simple, conventional word line drivers have often suffered from various complicating conditions. In this regard, bouncing (e.g., voltage ripples that can occur when a word line is pulled down from an activation voltage) and leakage currents (e.g., resultant from shorting adjacent word lines or word lines and adjacent bit lines) are examples of conditions that can damage memory cells, increase power consumption and/or result in improper operation. To prevent or otherwise mitigate the impacts of such conditions, various designs have been put forth for word line drivers. However, current designs often require relatively large area footprints due to the inclusion of a large number of transistors relative to the number of word lines. In other words, conventional word line drivers often take up a relatively large area and have a relatively high ratio of transistors to word lines.
FIG. 1 illustrates an example showing a conventional word line driver for a single word line (lwl0) in which the word line driver requires three transistors for a 3:1 ratio of transistors to word lines. FIG. 2 illustrates an alternative conventional word line driver for two word lines (lwl0 and lwl1), but for which five transistors (a 5:2 or 2.5:1 ratio) are required. The single word line driver of FIG. 1 is augmented in the example of FIG. 2 in order to support the provision of a word line driver capable of driving two word lines.
Accordingly, it may be desirable to provide an improved word line driver in terms of area consumption.